1. Field of the Invention
The present invention relates in general to a burst mode control circuit for a synchronous dynamic random access memory (referred to hereinafter as "synchronous DRAM"), and more particularly to a burst mode end detection unit for accurately detecting the end time of a burst mode.
2. Description of the Prior Art
Recently, a synchronous DRAM has been operated in a burst mode to enhance the data access time.
In the burst mode, data are sequentially written in memory cells in the synchronous DRAM which are externally designated. Also, the stored data are successively read out from the designated memory cells. At this time, the data are written or read on the basis of bursts of specified length.
In other words, in the burst mode, the synchronous DRAM receives a start address and an information (i.e., burst length) regarding the number of memory locations which are to be successively accessed. Also, addresses which are sequentially incremented by one from the start address are generated to sequentially access corresponding memory cells in the synchronous DRAM. At this time, the number of the generated addresses is defined by the burst length.
At the moment that the burst mode is ended, the synchronous DRAM must automatically be changed to a standby mode to receive a command regarding a new burst mode. Also, a line for inputting a row address strobe signal RAS must be precharged. Further, address counting, writing and reading operations must be stopped. To this end, the synchronous DRAM requires means which is capable of accurately detecting the end time of the burst mode.